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A low-power cache with successive tag comparison algorithm
In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (central processor unit), MCU (micro controller unit),...
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| Published in: | Current applied physics 2005, 5(3), , pp.227-230 |
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| Main Authors: | , , , |
| Format: | Article |
| Language: | English |
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| cited_by | cdi_FETCH-LOGICAL-c330t-16222f4671ceda7d49b9968499a0f8670add5e608bc2921054068f55c47738043 |
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| cites | cdi_FETCH-LOGICAL-c330t-16222f4671ceda7d49b9968499a0f8670add5e608bc2921054068f55c47738043 |
| container_end_page | 230 |
| container_issue | 3 |
| container_start_page | 227 |
| container_title | Current applied physics |
| container_volume | 5 |
| creator | Kim, Tae-Chan Kim, Chulwoo Chung, Bong-Young Kim, Soo-Won |
| description | In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (central processor unit), MCU (micro controller unit), cache, et cetera. This paper introduces a new low-power cache controller with successive tag comparison algorithm. Using these methods, the power consumption of a cache can be reduced. Simulation results show that the power consumption of a cache using the proposed method is reduced by 42% compared with conventional methods. |
| doi_str_mv | 10.1016/j.cap.2003.09.019 |
| format | article |
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| ispartof | Current Applied Physics, 2005, 5(3), , pp.227-230 |
| issn | 1567-1739 1878-1675 |
| language | eng |
| recordid | cdi_nrf_kci_oai_kci_go_kr_ARTI_105542 |
| source | ScienceDirect Freedom Collection 2022-2024 |
| subjects | Cache Low power consumption Successive tag algorithm 물리학 |
| title | A low-power cache with successive tag comparison algorithm |
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