Multiple Leading Zero Pattern Scheme for Non-volatile Memories

• Published in: Journal of semiconductor technology and science 2018, 18(2), 80, pp.246-254
• Main Authors: Choi, Ju Hee, Kwak, Jong Wook
• Format: Article
• Language: English
• Subjects: 전기공학
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2018.18.2.246

Non-volatile memories (NVMs) spend a significant energy to write data. To overcome the drawback of NVMs, researchers have proposed schemes to eliminate the unnecessary write operations by read-before-write scheme and they have achieved reducing the number of write operations. However, the importance of energy consumption of read operations is overlooked in their works, even though read access to NVM is also an important factor of the total power dissipation. To reduce the number of read operations of NVM, we propose a multiple leading zero pattern (MLZP) scheme by employing small tables which track and store the bit patterns frequently used. If another level of cache requires the data which the pattern table contains, the data is forwarded to the requestor from the pattern table instead of access to last-level cache (LLC). Since the size of pattern table is much smaller than that of the LLC, the total energy consumption for accesses to LLC is decreased. The simulation results show that 30.4% and 34.1% reduction in the total energy consumption are achieved compared to the previous works with STT-RAM and PCM, respectively. KCI Citation Count: 0