Novel Area-efficient Null Convention Logic based on CMOS and Gate Diffusion Input (GDI) Hybrid

Null convention logic (NCL) is a promising delay insensitive paradigm for constructing asynchronous circuits. Traditionally, NCL circuits are implemented utilizing complementary metal oxide semiconductor (CMOS) technology that has large area overhead. To address this issue, a HYBRID methodology is i...

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Bibliographic Details
Published in:Journal of semiconductor technology and science 2020, 20(1), 91, pp.127-134
Main Authors: Metku, Prashanthi, Kim, Kyung Ki, Choi, Minsu
Format: Article
Language:English
Subjects:
전기공학
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Summary:Null convention logic (NCL) is a promising delay insensitive paradigm for constructing asynchronous circuits. Traditionally, NCL circuits are implemented utilizing complementary metal oxide semiconductor (CMOS) technology that has large area overhead. To address this issue, a HYBRID methodology is introduced for realizing NCL circuits in this paper. The proposed approach utilizes both CMOS and gate diffusion input (GDI) techniques to significantly reduce the area. Compared with the conventional static CMOS NCL counterpart, the HYBRID implementation of an NCL up counter demonstrate an average of 10% reduction in the transistor count. KCI Citation Count: 2
ISSN:1598-1657
2233-4866
DOI:10.5573/JSTS.2020.20.1.127