Suppression of Parasitic Epitaxy Growth and Realization of High-Quality Wafer Surface Passivation of Silicon Heterojunction Solar Cells

Intrinsic hydrogenated amorphous silicon (i-a-Si:H) films lead to excellent surface passivation of crystalline silicon wafers. However, a-Si:H deposition on a crystalline silicon wafer often results in undesired epitaxy growth, which deteriorates the passivation property, In this paper, we studied t...

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Bibliographic Details
Published in:Journal of the Korean Physical Society 2020, 76(5), , pp.442-446
Main Authors: An, Jeong-Ho, Hong, Ji-Eun, Oh, Joon-Ho, Kong, Seong Ho, Kim, Ka-Hyun
Format: Article
Language:English
Subjects:
Amorphous silicon
Circuits
Crystal structure
Crystallinity
Dilution
Epitaxial growth
Gas pressure
Heterojunctions
Hydrogen storage
Mathematical and Computational Physics
Minority carriers
Particle and Nuclear Physics
Passivity
Photovoltaic cells
Physics
Physics and Astronomy
Plasma enhanced chemical vapor deposition
Silicon wafers
Solar cells
Theoretical
Wafers
물리학
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Summary:Intrinsic hydrogenated amorphous silicon (i-a-Si:H) films lead to excellent surface passivation of crystalline silicon wafers. However, a-Si:H deposition on a crystalline silicon wafer often results in undesired epitaxy growth, which deteriorates the passivation property, In this paper, we studied the influence of varying plasma enhanced chemical vapor deposition (PECVD) parameters, such as the product of the gas pressure (P) and the electrode distance ( D i) and the hydrogen dilution ratio (P = SiH 4 /(H 2 + SiH 4 ) × 100), on the passivation quality and the properties of silicon heterojunction (SHJ) solar cells. Measurements showed that proper combinations of high P × D i and large P values can yield high minority carrier lifetimes (MCLTs) of passivated silicon wafers. Also, the tendency of MCLTs measured from passivated wafers is the same as that for open circuit voltages ( V oc ) of fabricated SHJ solar cells. A high V oc is obtained from SHJ solar cells when unwanted epitaxial growth is minimized at the wafer surface.
ISSN:0374-4884
1976-8524
DOI:10.3938/jkps.76.442