Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

• Published in: Journal of semiconductor technology and science 2013, 13(3), 51, pp.224-236
• Main Authors: Narang, Rakhi, Saxena, Manoj, Gupta, R.S., Gupta, Mridula
• Format: Article
• Language: English
• Subjects: 전기공학
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/jsts.2013.13.3.224

This work presents a comparative study offour Double Gate tunnel FET (DG-TFET)architectures: conventional p-i-n DG-TFET, p-n-p-nDG-TFET, a gate dielectric engineered Heterogate(HG) p-i-n DG-TFET and a new device architecturewith the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, theproblem of high gate capacitance along with low ONcurrent for a p-i-n TFET, which severely hampers thecircuit performance of TFET can be overcome byusing a p-n-p-n TFET with a dielectric engineeredHetero-gate architecture (i.e. HG p-n-p-n). P-n-p-narchitecture improves the ON current and theheterogeneous dielectric helps in reducing the gatecapacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade theoutput characteristics, unlike the gate drain underlaparchitecture, and effectively reduces the gatecapacitance. KCI Citation Count: 24