Thermal Aware Buffer Insertion in the Early Stage of Physical Designs

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing;consequently, the timing violation occurs due to the m...

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Bibliographic Details
Published in:Journal of semiconductor technology and science 2012, 12(4), 48, pp.397-404
Main Authors: Kim, Jaehwan, Ahn, Byung-Gyu, Kim, Minbeom, Chong, Jongwha
Format: Article
Language:English
Subjects:
전기공학
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Summary:Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing;consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results. KCI Citation Count: 0
ISSN:1598-1657
2233-4866
DOI:10.5573/JSTS.2012.12.4.397