A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 μm CMOS

A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication)receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a s...

Full description

Saved in:
Bibliographic Details
Published in:Journal of semiconductor technology and science 2011, 11(1), 41, pp.59-64
Main Authors: Jaeyi Choi, Shin-Hyouk Seo, Hyunwon Moon, 남일구
Format: Article
Language:English
Subjects:
전기공학
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication)receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 m CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF)lower than 4.5 dB over the entire DSRC band. KCI Citation Count: 1
ISSN:1598-1657
2233-4866
DOI:10.5573/JSTS.2011.11.1.059