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Plasma immersion ion implantation for sub-22 nm node devices: FD-SOI and Tri-Gate

Here, we present and discuss the electrical characteristics of fully depleted MOSFET transistors of planar and tridimensional architecture, doped by Plasma Immersion Ion Implantation (PIII) or Beam Line Ion Implantation (BLII). Both techniques delivered similar and satisfactory results in considerin...

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Bibliographic Details
Main Authors: Duchaine, J., Milesi, F., Coquand, R., Barraud, S., Reboh, S., Gonzatti, F., Mazen, F., Torregrosa, Frank, CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 GRENOBLE Cedex 9, STMicroelectronics, 850, rue J. Monnet, 38926 Crolles, IBS, ZI Peynier-Rousset, Avenue Gaston Imbert prolongee, 13 790 Peynier
Format: Conference Proceeding
Language:English
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Summary:Here, we present and discuss the electrical characteristics of fully depleted MOSFET transistors of planar and tridimensional architecture, doped by Plasma Immersion Ion Implantation (PIII) or Beam Line Ion Implantation (BLII). Both techniques delivered similar and satisfactory results in considering the planar architecture. For tri-dimensional Tri-Gate transistors, the results obtained with PIII are superior.
ISSN:0094-243X
1551-7616
DOI:10.1063/1.4766492