Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process

• Published in: IEEE transactions on semiconductor manufacturing 2003-08, Vol.16 (3), p.486-500
• Main Authors: CHEN, Tung-Yang, KER, Ming-Dou
• Format: Article
• Language: English
• Subjects: Applied sciences; Channels; CMOS; CMOS process; Design. Technologies. Operation analysis. Testing; Devices; Diffusion; Drains; Electronics; Electrostatic discharge; Energy measurement; Exact sciences and technology; Fingers; Integrated circuits; Manufacturing processes; Microscopy; MOS devices; Protection; Robustness; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Static electricity; Studies; Transmission line measurements
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2003.815200

The layout dependence on ESD robustness of NMOS and PMOS devices has been experimentally investigated in details. A lot of CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection. The main layout parameters to affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate edge at drain and source regions, the spacing from the drain diffusion to the guard-ring diffusion, and the finger width of each unit finger. Non-uniform turn-on effects have been clearly investigated in the gate-grounded large-dimension NMOS devices by using EMMI (EMission MIcroscope) observation. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices. The relations between ESD robustness and the layout parameters have been explained by both transmission line pulsing (TLP) measured data and the energy band diagrams.