Mechanical effects of copper through-vias in a 3D die-stacked module

• Main Authors: Tanaka, N., Sato, T., Yamaji, Y., Morifuji, T., Umemoto, M., Takahashi, K.
• Format: Conference Proceeding
• Language: English
• Subjects: Applied sciences; Chemical vapor deposition; Copper; Design. Technologies. Operation analysis. Testing; Electronics; Etching; Exact sciences and technology; Fabrication; Insulation; Integrated circuits; Packaging; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Testing; Testing, measurement, noise and reliability; Thermal stresses; Wafer bonding
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2002.1008138

Mechanical effects of copper through-vias formed in silicon dies in a three dimensional module, in which four bare-dies with copper through-vias are vertically stacked and electrically connected through the copper-vias and metal bumps, were numerically and experimentally studied. To examine the mechanical effects caused by the existence of the copper through-vias in a rigid silicon-chip, a series of stress analyses, related simple mechanical tests, and reliability tests were carried out. All these results show that the copper through-via has unique effects on the stress distribution caused by thermal mismatch and on the interconnection reliability in the 3D die-stacked module. In particular, it was found that the developed micro copper through-via is reliable because the stress distribution due to thermal load is close to the hydrostatic pressure condition, and enhances chip-to-chip interconnection reliability because the copper-via restrains the plastic deformation of a gold bump during temperature cycling.