A novel stack capacitor cell for high density FeRAM compatible with CMOS logic

We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation barrier to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacit...

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Bibliographic Details
Main Authors: Hayashi, T., Igarashi, Y., Inomata, D., Ichimori, T., Mitsuhashi, T., Ashikaga, K., Ito, T., Yoshimaru, M., Nagata, M., Mitarai, S., Godaiin, H., Nagahama, T., Isobe, C., Moriya, H., Shoji, M., Ito, Y., Kuroda, H., Sasaki, M.
Format: Conference Proceeding
Language:English
Subjects:
Applied sciences
Capacitors
Circuit properties
CMOS logic circuits
CMOS technology
Design. Technologies. Operation analysis. Testing
Dielectric, amorphous and glass solid devices
Digital circuits
Electric, optical and optoelectronic circuits
Electrodes
Electronic circuits
Electronics
Exact sciences and technology
Ferroelectric films
Integrated circuits
Integrated circuits by function (including memories and processors)
Logic devices
Nonvolatile memory
Oxidation
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Tellurium
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Summary:We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation barrier to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacitors and no via contact cell scheme.
DOI:10.1109/IEDM.2002.1175899