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A Fail-Safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 μm CMOS I/O application

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Bibliographic Details
Main Authors: LIN, Jerry Heng-Chih, DUVVURY, Charvaka, HAROUN, Baher, OGUZMAN, Ismail, SOMAYAJI, Ananth
Format: Conference Proceeding
Language:English
Subjects:
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