Pel reconstruction on FPGA-augmented TriMedia

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2004-06, Vol.12 (6), p.622-635
• Main Authors: Sima, M., Cotofana, S.D., Vassiliadis, S., van Eijndhoven, J.T.J., Vissers, K.A.
• Format: Article
• Language: English
• Subjects: Application specific integrated circuits; Applied sciences; Coding, codes; Computation; Computer programs; Decoding; Design. Technologies. Operation analysis. Testing; Discrete cosine transforms; Electronics; Entropy; Exact sciences and technology; Field programmable gate arrays; Hardware; Information, signal and communications theory; Integrated circuits; Integrated circuits by function (including memories and processors); Inverse; Performance gain; Quantization; Reconstruction; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal and communications theory; Symbols; Telecommunications and information theory; Transform coding; Very large scale integration; VLIW
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2004.827594

This paper presents a TriMedia processor extended with three reconfigurable designs for entropy decoding (ED), inverse quantization (IQ), and two-dimensional (2-D) inverse discrete cosine transform (IDCT), and assesses the performance gain that is provided by such extensions when performing MPEG2-compliant pel reconstruction. We first describe an extension of the TriMedia architecture, which consists of a multiple-context field programmable gate array (FPGA)-based reconfigurable functional unit (RFU), a configuration unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the ED, IQ, and 2-D IDCT tasks, and propose to provide reconfigurable hardware support for a variable-length decoder that can decode two symbols per call (VLD-2), an inverse quantizer that can dequantize four coefficients per call (IQ-4), and an 1-D IDCT (1-D IDCT). The most important aspects concerning the implementation of the FPGA-mapped VLD-2, IQ-4, and 1-D IDCT units, as well as the organization of the software routines calling these FPGA-mapped computing units are outlined. Experimental results indicate that by configuring each of the VLD-2, IQ-4, and 1-D IDCT units on a different FPGA context, and by activating the contexts as needed, the FPGA-augmented TriMedia can perform MPEG2-compliant pel reconstruction with an average speed-up of 1.4/spl times/ over the standard TriMedia.