60nm gate length dual-Vt CMOS for high performance applications

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Bibliographic Details
Main Authors: MEHROTRA, M, WU, J, OLSEN, L, DELOACH, J, MEHIGAN, J, AGARWAL, R, WALSH, S, SEKEL, D, TSUNG, L, VAIDYANATHAN, M, TRENTMAN, B, LIU, K, JAIN, A, AUR, S, KHAMANKAR, R, NICOLLIAN, P, JIANG, Q, XU, Y, CAMPBELL, B, TINER, P, WISE, R, SCOTT, D, RODDER, M, LAAKSONEN, T, KIM, K, BATHER, W, KOSHY, R, CHEN, J, JACOBS, J, UKRAINTSEV, V
Format: Conference Proceeding
Language:English
Subjects:
Applied sciences
Electronics
Exact sciences and technology
Microelectronic fabrication (materials and surfaces technology)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Online Access:Get full text
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DOI:10.1109/VLSIT.2002.1015419