Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface

• Main Authors: Tsuchiya, R., Ohnishi, K., Horiuchi, M., Tsujikawa, S., Shimamoto, Y., Inada, N., Yugami, J., Ootsuka, F., Onai, T.
• Format: Conference Proceeding
• Language: English
• Subjects: Applied sciences; Boron; CMOS technology; Delay; Earth Observing System; Electronics; Exact sciences and technology; High K dielectric materials; High-K gate dielectrics; MOSFET circuits; Parasitic capacitance; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon compounds; Space technology; Transistors
• DOI: 10.1109/VLSIT.2002.1015429

We demonstrate 40-nm CMOS transistors for the 70-nm technology node. This transistor uses a high-k offset spacer (EOS: high-epsilon offset spacer) in achieving both a short-channel and high drivability along with SiN gate dielectrics with oxygen-enriched interface (OI-SiN) to suppress both the gate-leakage current and boron penetration. Consequently, N-MOSFET and P-MOSFET have high drive currents of 0.68 and 0.30 mA//spl mu/m, respectively, with I/sub off/=10 nA//spl mu/m, with an EOT value of 1.4 nm. The record gate delay of 280 fs (3.6 THz), for an N-MOSFET with the gate length of 19 nm, has also been achieved.