A dual-core 64-bit ultraSPARC microprocessor for dense server applications

• Published in: IEEE journal of solid-state circuits 2005-01, Vol.40 (1), p.7-18
• Main Authors: Takayanagi, T., Shin, J.L., Petrick, B., Su, J.Y., Levy, H., Ha Pham, Son, J., Moon, N., Bistry, D., Nair, U., Singh, M., Mathur, V., Leon, A.S.
• Format: Article
• Language: English
• Subjects: Amplifiers; Applied sciences; Blades; Buses (vehicles); Chip Multithreading (CMT); Circuit properties; CMOS technology; Computer networks; coupling noise; current-mode sense amplifier; deep-submicron technology; dense server; Design engineering; Design methodology; Design. Technologies. Operation analysis. Testing; Dielectrics; dual-core; ECC; Electric, optical and optoelectronic circuits; electromigration; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; hold time; Instability; Integrated circuits; Integrated circuits by function (including memories and processors); L2 Cache; Leakage; microprocessor; Microprocessors; multicore; multiprocessor; multithread; Negative bias temperature instability; negative bias temperature instability (NBTI); Network servers; Networks; Niobium compounds; Power dissipation; process variation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Servers; thread-level parallelism (TLP); translation look aside buffer (TLB); UltraSPARC
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2004.838023

A dual-core 64-bit microprocessor optimized for compute-dense systems such as rack-mount and blade servers for network computing was developed. The chip consists of two UltraSPARC II cores, each with its own 512 kB L2 cache, a DDR-1 memory controller, and symmetric multiprocessor bus (JBus) controllers. The 206-mm/sup 2/ die is fabricated in 0.13-/spl mu/m CMOS technology with seven layers of Cu and a low-k dielectric. The chip offers a highly efficient performance-per-watt ratio with a typical power dissipation of 23 W at 1.3 V and 1.2 GHz. A short design cycle was achieved by leveraging existing designs wherever possible and developing effective design methodologies and flows. Significant design challenges faced by this project are described. These include deep-submicron design issues, such as negative bias temperature instability (NBTI), leakage, coupling noise, intra-die process variation, and electromigration (EM). A second important design challenge was implementing a high-performance L2 cache subsystem with a short four-cycle core-to-L2 latency including ECC.