A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

An 8 M /spl times/ 32 GDDR (graphic DDR) SDRAM operating up to 800-MHz clock (CLK) frequency is described. The GDDR SDRAM demands an effective control of CAS latency due to the large and wide number of CAS latencies at the CLK frequency. A wave-pipelined CAS latency control circuit is proposed to pr...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2005-01, Vol.40 (1), p.223-232
Main Authors: LEE, Sang-Bo, JANG, Seong-Jin, KWAK, Jin-Seok, HWANG, Sang-Jun, JUN, Young-Hyun, CHO, Soo-In, LEE, Chil-Gee
Format: Article
Language:English
Subjects:
Activation
Applied sciences
Arrays
Banks
Bus efficiency
CAS latency
Circuits
Clocks
Content addressable storage
Degradation
Delay
Design. Technologies. Operation analysis. Testing
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Energy consumption
Exact sciences and technology
Frequency
graphic DDR SDRAM
Graphics
High speed
Integrated circuits
Integrated circuits by function (including memories and processors)
Marketing
partial activation
Power consumption
Random access memory
SDRAM
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Summary:An 8 M /spl times/ 32 GDDR (graphic DDR) SDRAM operating up to 800-MHz clock (CLK) frequency is described. The GDDR SDRAM demands an effective control of CAS latency due to the large and wide number of CAS latencies at the CLK frequency. A wave-pipelined CAS latency control circuit is proposed to provide stable operation for the large and wide number of CAS latencies. The increase of CAS latency also causes a degradation of data bus efficiency at high-speed operation due to the large gap between input data (DINs) and output data (DOUTs) at the operation of write followed by read. A gapless write to read scheme improves the data bus efficiency by separating write data-path from read data-path for different banks accesses. Partial array activation commands can reduce the peak current, preventing the reduction of the data retention time of DRAM cells at high-speed operation. The GDDR SDRAM operates successfully at the CLK frequency of 800 MHz at 2.1 V and 700 MHz at 1.8 V, respectively. The power consumption is measured to be /spl sim/2 W at 1.9 V.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2004.837983