A low-power highly digitized receiver for 2.4-GHz-band GFSK applications

This paper describes the design and measurement results of a low-power highly digitized receiver for Gaussian frequency-shift keying modulated input signals at 2.4 GHz. The RF front-end has been based on a low-IF architecture and does not require any variable gain or filtering blocks. The full dynam...

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Bibliographic Details
Published in:IEEE transactions on microwave theory and techniques 2005-02, Vol.53 (2), p.453-461
Main Authors: Bergveld, H.J., van Kaam, K.M.M., Leenaerts, D.M.W., Philips, K.J.P., Vaassen, A.W.P., Wetkzer, G.
Format: Article
Language:English
Subjects:
Applied sciences
Channels
Circuit properties
CMOS
CMOS integrated circuits (ICs)
demodulation
Digital
Digital modulation
digital signal processors
Digitization
Dynamic range
Electric, optical and optoelectronic circuits
Electronics
Exact sciences and technology
Filtering
Filtration
Frequency measurement
Frequency modulation
Frequency shift keying
Gain
Matched filters
Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits
Radio frequency
Receivers
sigma-delta modulation
Signal design
UHF receivers
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Summary:This paper describes the design and measurement results of a low-power highly digitized receiver for Gaussian frequency-shift keying modulated input signals at 2.4 GHz. The RF front-end has been based on a low-IF architecture and does not require any variable gain or filtering blocks. The full dynamic range of the low-IF signal is converted into the digital domain by a low-power high-resolution time-continuous SigmaDelta analog-to-digital converter (ADC). This leads to a linear receive chain without limiters. A fifth-order poly-phase loop filter is used in the complex SigmaDelta ADC. The digital block performs filtering and demodulation. Channel filtering is combined with matched filtering and the suppression of noise resulting from the SigmaDelta ADC. The high degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. The receiver has been realized in a standard 0.18-mum CMOS process and measures 3.5 mm 2 . The only external components are an antenna filter and a crystal. The power consumption is only 32 mW in the continuous mode, which is at least a factor of two lower than state-of-the-art CMOS receivers
ISSN:0018-9480
1557-9670
DOI:10.1109/TMTT.2004.840756