Three-dimensional simulation of realistic single electron transistors

• Published in: IEEE transactions on nanotechnology 2005-07, Vol.4 (4), p.415-421
• Main Authors: Fiori, G., Pala, M.G., Iannaccone, G.
• Format: Article
• Language: English
• Subjects: Applied sciences; Boundary conditions; Computational modeling; Computer simulation; Density functional theory; Devices; Electronics; Electrons; Exact sciences and technology; Gallium arsenide; Molecular electronics, nanoelectronics; Nanomaterials; Nanoscale devices; Nanostructure; Poisson/SchrÖdinger; Potential well; Quantum computing; Quantum confinement; Schrodinger equation; Schroedinger equation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; silicon-on-insulator (SOI) technology; Single electron transistors; single electron transistors (SETs); split gates; three-dimensional (3-D) solver; Transistors
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2005.851284

We present an approach, and its implementation in a computer program, for the three-dimensional (3-D) simulation of realistic single electron transistor (SET) structures, in which subregions with different degrees of quantum confinement are simultaneously considered. The proposed approach is based on the self-consistent solution of the many body Schrodinger equation with density functional theory and on the computation of the conductance of tunnel constrictions through the solution of the 3-D Schrodinger equation with open boundary conditions. We have developed an efficient code (ViDES) based on such an approach. As examples of addressable SET structures, we present the simulation of a SET, one defined by metal gates on an AlGaAs/GaAs heterostructures, and of a SET defined by etching and oxidation on the silicon-on-insulator material system. Since SETs represent prototypical nanoscale devices, the code may be a valuable tool for the investigation and optimization of a broad range of nanoelectronic solid-state devices.