Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements

Mathematical morphology operations are applied in many real-time applications, such as video segmentation. For real-time requirement, efficient hardware implementation is necessary. This paper proposes a new architecture named Partial-Result-Reuse (PRR) architecture for mathematical morphological op...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology 2005-09, Vol.15 (9), p.1156-1169
Main Authors: CHIEN, Shao-Yi, MA, Shyh-Yih, CHEN, Liang-Gee
Format: Article
Language:English
Subjects:
Applied sciences
Architecture
Cost engineering
Costs
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Hardware
Image coding
Image processing
Image segmentation
Information, signal and communications theory
Integrated circuits
Integrated circuits by function (including memories and processors)
Marketing
Mathematical analysis
Mathematical morphology
Morphological operations
Morphology
morphology architecture
partial-result-reuse (PRR)
Real time
Segmentation
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Shape
Signal processing
Systolic arrays
Telecommunications and information theory
Video compression
video segmentation
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Summary:Mathematical morphology operations are applied in many real-time applications, such as video segmentation. For real-time requirement, efficient hardware implementation is necessary. This paper proposes a new architecture named Partial-Result-Reuse (PRR) architecture for mathematical morphological operations with flat structuring elements. Partial results generated during calculation process are kept and reused in this architecture to reduce hardware cost. With PRR concept and self-affinity property of structuring elements, the proposed architecture is more cost-effective and more general than existing morphology architectures. Moreover, it can be combined with systolic array to give consideration to both flexibility and hardware cost. We also propose a methodology to generate PRR architecture. With graphic method, the PRR architecture can be easily generated, and it can deal with structuring elements of any shape. The very large scale integration implementation of the PRR architecture shows that the area of processing element is small and can be fully piplelined without large overhead. The maximum frequency of the chip is 200 MHz in simulation, while processing speed of 550 morphological operations/s on a 720/spl times/480 frame can be achieved.
ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2005.852622