Design and development of 130-nanometer ICs for a multi-Gigabit switching network system

• Main Authors: Khan, A., Ruparel, K., Joly, C., Ghanta, V., Le, D., Nguyen, T., Yu, J., Yang, S., Ahmed, I., Burnside, N., Chagarlamudi, V., Cheung, M., Chiu, F., Fan, Y., Ge, D., Gill, J., Huang, P., Jayapal, V., Kim, O., Li, M., Mak, H., McKeever, P., Nguyen, S., Rajan, K., Riley, S., Tran, P., Truong, H., Tsou, A., Wang, D., Yang, C., Zhang, J., Zhong, X.
• Format: Conference Proceeding
• Language: English
• Subjects: Applied sciences; Assembly systems; Buffer storage; Circuit properties; CMOS process; Control systems; Design methodology; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Engines; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Packaging; Packet switching; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal design; Switching, multiplexing, switched capacity circuits; Throughput; Transistors
• DOI: 10.1109/CICC.2004.1358809

A system-centric, fully-hierarchical design methodology and design techniques developed to create four ICs, which provide the core functionality of a multi-Gigabit switching network system, are presented. The system is capable of switching more than 500 million packets per second. Electrical and physical design methods for one IC are described. /spl sim/76 M transistors are integrated in a 130 nm CMOS 8-metal process. Functional and electrical design requirements were achieved with the first silicon.