Test power reduction with multiple capture orders

• Main Authors: LEE, Kuen-Jong, HSU, Shaing-Jer, HO, Chia-Ming
• Format: Conference Proceeding
• Language: English
• Subjects: Applied sciences; Benchmark testing; Circuit faults; Circuit testing; Design methodology; Design. Technologies. Operation analysis. Testing; Electronics; Energy consumption; Exact sciences and technology; Integrated circuits; Interleaved codes; Logic; Power dissipation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; System-on-a-chip; Test pattern generators
• ISSN: 1081-7735; 2377-5386
• DOI: 10.1109/ATS.2004.82

This paper proposes a method to reduce the excess power dissipation during scan testing. The proposed method divides a scan chain into a number of sub-chains, and enables only one sub-chain at a time for both the scan and capture operations. To efficiently deal with the data dependence problem during the capture cycles, we develop a multiple-capture-orders method to guarantee the full scan fault coverage. A test pattern generation procedure is developed to reduce the test application time and a test architecture based on a ring control structure is adopted which makes the test control very simple and requires very low area overhead. Experimental results for large ISCAS'89 benchmark circuits show that the proposed method can reduce average and peak power by 86.8% and 66.1% in average, respectively, when 8 sub-chains are used.