Testing for missing-gate faults in reversible circuits

• Main Authors: Hayes, J.P., Polian, I., Becker, B.
• Format: Conference Proceeding
• Language: English
• Subjects: Application software; Applied sciences; Circuit faults; Circuit properties; Circuit simulation; Circuit testing; Computer architecture; design for test; Design for testability; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electrical fault detection; Electronic circuits; Electronics; Exact sciences and technology; Fault detection; fault models; Integrated circuits; Laboratories; missing gate faults; quantum circuits; Quantum computing; Reversible circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Testing, measurement, noise and reliability
• ISSN: 1081-7735; 2377-5386
• DOI: 10.1109/ATS.2004.84

Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the characteristics of k-CNOT circuits and observe that traditional fault models like the stuck-at model may not accurately represent their faulty behavior or test requirements. A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies. It is shown that MGFs are highly testable, and that all MGFs in an N-gate k-CNOT circuit can be detected with from one to [N/2] test vectors. A design-for-test (DFT) method to make an arbitrary circuit fully testable for MGFs using a single test vector is described. Finally, we present simulation results to determine (near) optimal test sets and DFT configurations for some benchmark circuits.