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A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS
This paper describes a 16 /spl times/ 16 bit single-cycle 2's complement multiplier with a reconfigurable PLA control block fabricated in 90-nm dual-V/sub t/ CMOS technology, operating at 1 GHz, 9 mW (measured at 1.3 V, 50/spl deg/C). Optimally tiled compressor tree architecture with radix-4 Bo...
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Published in: | IEEE journal of solid-state circuits 2006-01, Vol.41 (1), p.256-264 |
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Main Authors: | , , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | This paper describes a 16 /spl times/ 16 bit single-cycle 2's complement multiplier with a reconfigurable PLA control block fabricated in 90-nm dual-V/sub t/ CMOS technology, operating at 1 GHz, 9 mW (measured at 1.3 V, 50/spl deg/C). Optimally tiled compressor tree architecture with radix-4 Booth encoding, arrival-profile aware completion adder and low clock power write-port flip-flop circuits enable a dense layout occupying 0.03 mm/sup 2/ while simultaneously achieving: 1) low compressor tree fan-outs and wiring complexity; 2) low active leakage power of 540 /spl mu/W and high noise tolerance with all high-V/sub t/ usage; 3) ultra low standby-mode power of 75 /spl mu/W and fast wake-up time of |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2005.859893 |