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A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS
This paper describes a 16 /spl times/ 16 bit single-cycle 2's complement multiplier with a reconfigurable PLA control block fabricated in 90-nm dual-V/sub t/ CMOS technology, operating at 1 GHz, 9 mW (measured at 1.3 V, 50/spl deg/C). Optimally tiled compressor tree architecture with radix-4 Bo...
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| Published in: | IEEE journal of solid-state circuits 2006-01, Vol.41 (1), p.256-264 |
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| Main Authors: | , , , , , , |
| Format: | Article |
| Language: | English |
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| cites | cdi_FETCH-LOGICAL-c383t-edb5d4fefcc98b1fb6a0f50d7b6ee036b60619ba314964f8d8aa9f0b145b55923 |
| container_end_page | 264 |
| container_issue | 1 |
| container_start_page | 256 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 41 |
| creator | Hsu, S.K. Mathew, S.K. Anders, M.A. Zeydel, B.R. Oklobdzija, V.G. Krishnamurthy, R.K. Borkar, S.Y. |
| description | This paper describes a 16 /spl times/ 16 bit single-cycle 2's complement multiplier with a reconfigurable PLA control block fabricated in 90-nm dual-V/sub t/ CMOS technology, operating at 1 GHz, 9 mW (measured at 1.3 V, 50/spl deg/C). Optimally tiled compressor tree architecture with radix-4 Booth encoding, arrival-profile aware completion adder and low clock power write-port flip-flop circuits enable a dense layout occupying 0.03 mm/sup 2/ while simultaneously achieving: 1) low compressor tree fan-outs and wiring complexity; 2) low active leakage power of 540 /spl mu/W and high noise tolerance with all high-V/sub t/ usage; 3) ultra low standby-mode power of 75 /spl mu/W and fast wake-up time of |
| doi_str_mv | 10.1109/JSSC.2005.859893 |
| format | article |
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Optimally tiled compressor tree architecture with radix-4 Booth encoding, arrival-profile aware completion adder and low clock power write-port flip-flop circuits enable a dense layout occupying 0.03 mm/sup 2/ while simultaneously achieving: 1) low compressor tree fan-outs and wiring complexity; 2) low active leakage power of 540 /spl mu/W and high noise tolerance with all high-V/sub t/ usage; 3) ultra low standby-mode power of 75 /spl mu/W and fast wake-up time of <1 cycle using PMOS sleep transistors; 4) scalable multiplier performance up to 1.5 GHz, 32 mW measured at 1.95 V, 50/spl deg/C, and (v) low-voltage mode multiplier performance of 50 MHz, 79/spl mu/W measured at 570 mV, 50/spl deg/C.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2005.859893</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>2's complement ; Adders ; Applied sciences ; Booth encoding ; Circuit properties ; Circuits ; Clocks ; CMOS ; CMOS technology ; Complement ; Compressors ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Encoding ; Exact sciences and technology ; flip-flop ; Flip-flops ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; multiplier ; Multipliers ; Noise measurement ; Power measurement ; programmable logic array (PLA) ; Programmable logic arrays ; radix-4 ; reconfigurable ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Sleep ; sleep transistor ; Time measurement ; Transistors ; Trees</subject><ispartof>IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.256-264</ispartof><rights>2006 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c383t-edb5d4fefcc98b1fb6a0f50d7b6ee036b60619ba314964f8d8aa9f0b145b55923</citedby><cites>FETCH-LOGICAL-c383t-edb5d4fefcc98b1fb6a0f50d7b6ee036b60619ba314964f8d8aa9f0b145b55923</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1564366$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,780,784,789,790,4050,4051,23930,23931,25140,27924,27925,54796</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=17481982$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Hsu, S.K.</creatorcontrib><creatorcontrib>Mathew, S.K.</creatorcontrib><creatorcontrib>Anders, M.A.</creatorcontrib><creatorcontrib>Zeydel, B.R.</creatorcontrib><creatorcontrib>Oklobdzija, V.G.</creatorcontrib><creatorcontrib>Krishnamurthy, R.K.</creatorcontrib><creatorcontrib>Borkar, S.Y.</creatorcontrib><title>A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper describes a 16 /spl times/ 16 bit single-cycle 2's complement multiplier with a reconfigurable PLA control block fabricated in 90-nm dual-V/sub t/ CMOS technology, operating at 1 GHz, 9 mW (measured at 1.3 V, 50/spl deg/C). Optimally tiled compressor tree architecture with radix-4 Booth encoding, arrival-profile aware completion adder and low clock power write-port flip-flop circuits enable a dense layout occupying 0.03 mm/sup 2/ while simultaneously achieving: 1) low compressor tree fan-outs and wiring complexity; 2) low active leakage power of 540 /spl mu/W and high noise tolerance with all high-V/sub t/ usage; 3) ultra low standby-mode power of 75 /spl mu/W and fast wake-up time of <1 cycle using PMOS sleep transistors; 4) scalable multiplier performance up to 1.5 GHz, 32 mW measured at 1.95 V, 50/spl deg/C, and (v) low-voltage mode multiplier performance of 50 MHz, 79/spl mu/W measured at 570 mV, 50/spl deg/C.</description><subject>2's complement</subject><subject>Adders</subject><subject>Applied sciences</subject><subject>Booth encoding</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>Clocks</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>Complement</subject><subject>Compressors</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Encoding</subject><subject>Exact sciences and technology</subject><subject>flip-flop</subject><subject>Flip-flops</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>multiplier</subject><subject>Multipliers</subject><subject>Noise measurement</subject><subject>Power measurement</subject><subject>programmable logic array (PLA)</subject><subject>Programmable logic arrays</subject><subject>radix-4</subject><subject>reconfigurable</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Sleep</subject><subject>sleep transistor</subject><subject>Time measurement</subject><subject>Transistors</subject><subject>Trees</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><recordid>eNp9kU1LAzEQhoMoWD_ugpcgqKetk80mTY5l0VaptFBFbyHZTSSy3a1J9-C_N6UFwYOnYZjnfWF4ELogMCQE5N3TclkOcwA2FEwKSQ_QgDAmMjKi74doAEBEJtP9GJ3E-JnWohBkgKZjnOJ4Ml8s794w4ZnxG7zqm41fN94GrNsaB1t1rfMffdCmsXgxG-Om69bYt1hC1q5w-TxfnqEjp5toz_fzFL0-3L-U02w2nzyW41lWUUE3ma0NqwtnXVVJYYgzXINjUI8MtxYoNxw4kUZTUkheOFELraUDQwpmGJM5PUW3u9516L56Gzdq5WNlm0a3tuujEjLlgeQikTf_krkAyKUYJfDqD_jZ9aFNXyhJcpBAc5Ig2EFV6GIM1ql18CsdvhUBtTWgtgbU1oDaGUiR632vjpVuXNBt5eNvbpQMSLF96XLHeWvt75nxgnJOfwBLaIqS</recordid><startdate>200601</startdate><enddate>200601</enddate><creator>Hsu, S.K.</creator><creator>Mathew, S.K.</creator><creator>Anders, M.A.</creator><creator>Zeydel, B.R.</creator><creator>Oklobdzija, V.G.</creator><creator>Krishnamurthy, R.K.</creator><creator>Borkar, S.Y.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>200601</creationdate><title>A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS</title><author>Hsu, S.K. ; Mathew, S.K. ; Anders, M.A. ; Zeydel, B.R. ; Oklobdzija, V.G. ; Krishnamurthy, R.K. ; Borkar, S.Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c383t-edb5d4fefcc98b1fb6a0f50d7b6ee036b60619ba314964f8d8aa9f0b145b55923</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2006</creationdate><topic>2's complement</topic><topic>Adders</topic><topic>Applied sciences</topic><topic>Booth encoding</topic><topic>Circuit properties</topic><topic>Circuits</topic><topic>Clocks</topic><topic>CMOS</topic><topic>CMOS technology</topic><topic>Complement</topic><topic>Compressors</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Encoding</topic><topic>Exact sciences and technology</topic><topic>flip-flop</topic><topic>Flip-flops</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>multiplier</topic><topic>Multipliers</topic><topic>Noise measurement</topic><topic>Power measurement</topic><topic>programmable logic array (PLA)</topic><topic>Programmable logic arrays</topic><topic>radix-4</topic><topic>reconfigurable</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Sleep</topic><topic>sleep transistor</topic><topic>Time measurement</topic><topic>Transistors</topic><topic>Trees</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Hsu, S.K.</creatorcontrib><creatorcontrib>Mathew, S.K.</creatorcontrib><creatorcontrib>Anders, M.A.</creatorcontrib><creatorcontrib>Zeydel, B.R.</creatorcontrib><creatorcontrib>Oklobdzija, V.G.</creatorcontrib><creatorcontrib>Krishnamurthy, R.K.</creatorcontrib><creatorcontrib>Borkar, S.Y.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Hsu, S.K.</au><au>Mathew, S.K.</au><au>Anders, M.A.</au><au>Zeydel, B.R.</au><au>Oklobdzija, V.G.</au><au>Krishnamurthy, R.K.</au><au>Borkar, S.Y.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2006-01</date><risdate>2006</risdate><volume>41</volume><issue>1</issue><spage>256</spage><epage>264</epage><pages>256-264</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper describes a 16 /spl times/ 16 bit single-cycle 2's complement multiplier with a reconfigurable PLA control block fabricated in 90-nm dual-V/sub t/ CMOS technology, operating at 1 GHz, 9 mW (measured at 1.3 V, 50/spl deg/C). Optimally tiled compressor tree architecture with radix-4 Booth encoding, arrival-profile aware completion adder and low clock power write-port flip-flop circuits enable a dense layout occupying 0.03 mm/sup 2/ while simultaneously achieving: 1) low compressor tree fan-outs and wiring complexity; 2) low active leakage power of 540 /spl mu/W and high noise tolerance with all high-V/sub t/ usage; 3) ultra low standby-mode power of 75 /spl mu/W and fast wake-up time of <1 cycle using PMOS sleep transistors; 4) scalable multiplier performance up to 1.5 GHz, 32 mW measured at 1.95 V, 50/spl deg/C, and (v) low-voltage mode multiplier performance of 50 MHz, 79/spl mu/W measured at 570 mV, 50/spl deg/C.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2005.859893</doi><tpages>9</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.256-264 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_pascalfrancis_primary_17481982 |
| source | IEEE Electronic Library (IEL) Journals |
| subjects | 2's complement Adders Applied sciences Booth encoding Circuit properties Circuits Clocks CMOS CMOS technology Complement Compressors Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Encoding Exact sciences and technology flip-flop Flip-flops Integrated circuits Integrated circuits by function (including memories and processors) multiplier Multipliers Noise measurement Power measurement programmable logic array (PLA) Programmable logic arrays radix-4 reconfigurable Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sleep sleep transistor Time measurement Transistors Trees |
| title | A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS |
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