High-level synthesis: an essential ingredient for designing complex ASICs

It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog incurs a performance penalty. The case study here shows that this need not be the case. If the higher-level language has suitable semantics, it is possible to synthesize hardware that is competitive with hand-...

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Bibliographic Details
Main Authors: Arvind, Nikhil, Rishiyur S., Rosenband, Daniel L., Dave, Nirav
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Applied sciences
Clocks
CMOS technology
Computer aided design
Computer science
control theory
systems
Costs
Design methodology
Electronics
Exact sciences and technology
Hardware design languages
High level synthesis
Integrated circuits
Integrated circuits by function (including memories and processors)
Microarchitecture
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Software
Software libraries
Testing
Online Access:Request full text
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Summary:It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog incurs a performance penalty. The case study here shows that this need not be the case. If the higher-level language has suitable semantics, it is possible to synthesize hardware that is competitive with hand-written Verilog RTL. Differences in the hardware quality are dominated by architecture differences and, therefore, it is more important to explore multiple hardware architectures. This exploration is not practical without quality synthesis from higher-level languages.
ISSN:1092-3152
1558-2434
DOI:10.1109/ICCAD.2004.1382681