New gate oxide wear-out model for accurate device lifetime projections on vertical drain NMOSFET

In this paper, the reliability of the vertical drain NMOS (VDNMOS) device structure has been evaluated for a state of the art CMOS process. In past technologies, reliability was restricted by hot carrier degradation effects. With technology scaling, gate oxide wear-out has become the reliability lim...

Full description

Saved in:
Bibliographic Details
Main Authors: Pae, S., Agostinelli, M., Curello, G., Lau, S., Ramey, S., Alavi, M.
Format: Conference Proceeding
Language:English
Subjects:
Applied sciences
Breakdown voltage
CMOS process
CMOS technology
Degradation
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Hot carriers
Integrated circuits
Low voltage
MOS devices
MOSFET circuits
Semiconductor device modeling
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Stress
Transistors
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, the reliability of the vertical drain NMOS (VDNMOS) device structure has been evaluated for a state of the art CMOS process. In past technologies, reliability was restricted by hot carrier degradation effects. With technology scaling, gate oxide wear-out has become the reliability limiter. A new VDNMOS oxide wear-out model has been developed and verified with low voltage stress data. This new model accurately captures the dependence of VDNMOS lifetime on drain to gate bias and can be used to better project the maximum drain voltage at operating condition.
DOI:10.1109/IRWS.2004.1422730