Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs

• Published in: IEEE electron device letters 2006-08, Vol.27 (8), p.692-695
• Main Authors: Gili, E., Uchino, T., Hakim, M.M.A., de Groot, C.H., Buiu, O., Hall, S., Ashburn, P.
• Format: Article
• Language: English
• Subjects: Anisotropic magnetoresistance; Applied sciences; Channels; CMOS; CMOS process; CMOS technology; Compound structure devices; Contact; Design. Technologies. Operation analysis. Testing; Diffusion; drain-induced barrier lowering (DIBL); Drains; Dry etching; Electronics; Epitaxial growth; Exact sciences and technology; Fabrication; Integrated circuits; Ion implantation; junction; Lithography; Microelectronic fabrication (materials and surfaces technology); MOSFETs; Pillars; Plasma applications; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Spacers; Transistors; vertical MOSFET
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2006.879031

A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible and, hence, facilitates the integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a subthreshold slope of 95 mV/dec (at V DS =1 V) and a drain-induced barrier lowering of 0.12 V