Characteristics and modeling of sub-10-nm planar bulk CMOS devices fabricated by lateral source/drain junction control : Advanced compact models and 45-nm modeling challenges

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Bibliographic Details
Published in:IEEE transactions on electron devices 2006, Vol.53 (9), p.1961-1970
Main Authors: WAKABAYASHI, Hitoshi, EZAKI, Tatsuya, YAMAMOTO, Toyoji, HANE, Masami, MOGAMI, Tohru, SAKAMOTO, Toshitsugu, KAWAURA, Hisao, IKARASHI, Nobuyuki, IKEZAWA, Nobuyuki, NARIHIRO, Mitsuru, OCHIAI, Yukinori, IKEZAWA, Takeo, TAKEUCHI, Kiyoshi
Format: Article
Language:English
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
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ISSN:0018-9383
1557-9646