An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing

Current and future integrated systems demand cost-effective test solutions. In response to that need, this work presents a very compact mixed-signal test system. It performs the characterization of the magnitude and phase responses over frequency at multiple nodes of an analog circuit. The control i...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2006-10, Vol.41 (10), p.2301-2313
Main Authors: Valdes-Garcia, A., Hussien, F.A.-L., Silva-Martinez, J., Sanchez-Sinencio, E.
Format: Article
Language:English
Subjects:
algorithmic ADC
Algorithms
Analog circuits
analog multiplier
Analog testing
Applied sciences
Automatic control
Automatic test equipment
Automatic testing
built-in testing
Circuit properties
Circuit testing
CMOS circuits
CMOS technology
Control systems
Demand
design for testability
Design. Technologies. Operation analysis. Testing
Digital
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Frequency response
Integrated circuits
multivibrator
Oscillators, resonators, synthetizers
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
System testing
System-on-a-chip
Test systems
Testing, measurement, noise and reliability
Tuning
Voltage controlled oscillators
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Summary:Current and future integrated systems demand cost-effective test solutions. In response to that need, this work presents a very compact mixed-signal test system. It performs the characterization of the magnitude and phase responses over frequency at multiple nodes of an analog circuit. The control inputs and output of this system are digital, enabling the test of the analog components in a system-on-chip (SoC) or system-in-package (SiP) through a low-cost digital automatic test equipment. Robust and area-efficient building blocks are proposed for the implementation of the test system, including a linearized analog multiplier for accurate magnitude and phase detection, a wide tuning range voltage-controlled oscillator and a low-power algorithmic analog-to-digital converter. Their individual design considerations and performance results are presented. A complete prototype in TSMC CMOS 0.35-mum technology employs only 0.3mm 2 of area. The operation of this test system is demonstrated by performing frequency response characterizations up to 130 MHz at various nodes of two different fourth-order continuous-time filters integrated in the same chip
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2006.881561