VirtualScan: a new compressed scan technology for test cost reduction

This work describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are g...

Full description

Saved in:
Bibliographic Details
Main Authors: Wang, L.-T., Xiaoqing Wen, Furukawa, H., Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai, Abdel-Hafez, K.S., Shianling Wu
Format: Conference Proceeding
Language:English
Subjects:
Applied sciences
Automatic test pattern generation
Automatic testing
Built-in self-test
Circuit faults
Circuit testing
Costs
Electronic equipment testing
Electronics
Exact sciences and technology
Integrated circuit testing
Manufacturing
System testing
Testing, measurement, noise and reliability
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This work describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction.
DOI:10.1109/TEST.2004.1387356