Minimization of Parasitic Inductances in SFQ Circuits Using Over- and Under-Ground Planes

• Published in: IEEE transactions on applied superconductivity 2007-06, Vol.17 (2), p.462-465
• Main Authors: Myoren, H., Kishita, N., Taino, T., Takada, S.
• Format: Article
• Language: English
• Subjects: 2-branch D-FF; Applied sciences; Circuit properties; Circuit simulation; Circuits; Counting circuits; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electrical engineering. Electrical power engineering; Electrodes; Electronic circuits; Electronics; Exact sciences and technology; Ground plane; Inductance; Inductors; Integrated circuits; Josephson junctions; Large-scale systems; Magnetic devices; Minimization; National electric code; Niobium; Optimization; Over- and under-ground planes; parasitic inductance; Planes; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SFQ logic circuits; Superconductivity; Transformers and inductors
• ISSN: 1051-8223; 1558-2515
• DOI: 10.1109/TASC.2007.898053

We designed the single-flux-quantum (SFQ) circuits that were fabricating using the NEC 2.5 kA/cm 2 standard process that has four Nb layers. Before designing circuits with two ground planes, we estimated sheet inductances of the base and counter planes using simple rectangular-shape inductors. Estimated sheet inductance of the base plane was 0.75 of the original value for the circuits with only under-ground plane. For the counter plane, sheet inductance was estimated to be 0.55 of the original value. We designed a 2-branch D-FF gate and fabricated SFQ circuits including the 2-branch D-FF using the NEC standard process. Parasitic inductances of the counter layer in the 2-branch D-FF were effectively minimized using two ground planes and frequency dependences of the lower bias margin were improved.