Enabling compiler flow for embedded VLIW DSP processors with distributed register files

High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in designs of VLIW DSP processors, distributed register files and multi-bank register architectures are being adopted to eliminat...

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Bibliographic Details
Published in:ACM SIGPLAN Notices 2007-07, Vol.42 (7), p.146-148
Main Authors: CHEN, Chung-Kai, TSENG, Ling-Hua, CHEN, Shih-Chang, LIN, Young-Jia, YOU, Yi-Ping, LU, Chia-Han, LEE, Jenq-Kuen
Format: Article
Language:English
Subjects:
Applied sciences
Computer science
control theory
systems
Computer systems and distributed systems. User interface
Exact sciences and technology
Language theory and syntactical analysis
Programming languages
Software
Theoretical computing
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Summary:High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in designs of VLIW DSP processors, distributed register files and multi-bank register architectures are being adopted to eliminate the amount of read/write ports in register files. This presents new challenges for devising compiler optimization schemes for such architectures. In this paper, we address the compiler optimization issues for PAC architecture, which is a 5-way issue DSP processor with distributed register files. We present an integrated flow to address several phases of compiler optimizations in interacting with distributed register files and multi-bank register files in the layer of instruction scheduling, software pipelining, and data flow optimizations. Our experiments on a novel 32-bit embedded VLIW DSP (known as the PAC DSP core) exhibit the state of the art performance for embedded VLIW DSP processors with distributed register files by incorporating our proposed schemes in compilers.
ISSN:1523-2867
0362-1340
1558-1160
DOI:10.1145/1273444.1254793