Advanced backside failure analysis in 65 nm CMOS technology

Due to reducing size of elementary devices, increasing number of metallization levels and decreasing of power supply voltage, the debug and failure analysis of advanced CMOS designs requires the implementation of specific backside sample preparation methodologies and backside measurement flow. This...

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Bibliographic Details
Published in:Microelectronics and reliability 2007-08, Vol.47 (9), p.1550-1554
Main Authors: Bianic, Stephane, Allemand, Stéphanie, Kerrosa, Grégory, Scafidi, Pascal, Renard, Didier
Format: Article
Language:English
Subjects:
Applied sciences
Circuit properties
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Testing, measurement, noise and reliability
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Summary:Due to reducing size of elementary devices, increasing number of metallization levels and decreasing of power supply voltage, the debug and failure analysis of advanced CMOS designs requires the implementation of specific backside sample preparation methodologies and backside measurement flow. This paper describes the diagnosis and backside failure analysis flow implemented to successfully debug a flip-flop cell designed in 65 nm CMOS technology.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2007.07.076