A 5-ns 1-Mb ECL BiCMOS SRAM

A 1-Mword*1-b ECL (emitter coupled logic) 10 K I/O (input/output) compatible SRAM (static random-access memory) with 5-ns typical address access time has been developed using double-level poly-Si, double-level metal, 0.8- mu m BiCMOS technology. To achieve 5-ns address access time, high-speed X-addr...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1990-10, Vol.25 (5), p.1057-1062
Main Authors: Takada, M., Nakamura, K., Takeshima, T., Furuta, K., Yamazaki, T., Imai, K., Ohi, S., Sekine, Y., Minato, Y., Kimuto, H.
Format: Article
Language:English
Subjects:
Applied sciences
BiCMOS integrated circuits
Decoding
Delay effects
Driver circuits
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
MOSFET circuits
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal processing
SRAM chips
Voltage
Wiring
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Summary:A 1-Mword*1-b ECL (emitter coupled logic) 10 K I/O (input/output) compatible SRAM (static random-access memory) with 5-ns typical address access time has been developed using double-level poly-Si, double-level metal, 0.8- mu m BiCMOS technology. To achieve 5-ns address access time, high-speed X-address decoding circuits with wired-OR predecoders and ECL-to-CMOS voltage-level converters with partial address decoding function and sensing circuits with small differential signal voltage swing were developed. The die and memory cell sizes are 16.8 mm*6.7 mm and 8.5 mu m*5.3 mu m, respectively. The active power is 1 W at 100-MHz operation.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.62124