Practical Asynchronous Interconnect Network Design

The implementation of interconnect is becoming a significant challenge in modern integrated circuit (IC) design. Both synchronous and asynchronous strategies have been suggested to manage this problem. Creating a low skew clock tree for synchronous inter-block pipeline stages is a significant challe...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2008-05, Vol.16 (5), p.579-588
Main Authors: Quinton, B.R., Greenstreet, M.R., Wilton, S.J.E.
Format: Article
Language:English
Subjects:
Application specific integrated circuits
Applied sciences
Asynchronous logic circuits
Circuit properties
Clocks
Delay
Design automation
Design engineering
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuit interconnections
Integrated circuits
interconnection networks
Network-on-a-chip
network-on-chip (NoC)
Pipeline processing
Pipelines
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Strategy
Studies
Synchronous
System-on-a-chip
system-on-chip (SoC)
Throughput
Very large scale integration
Wire
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Summary:The implementation of interconnect is becoming a significant challenge in modern integrated circuit (IC) design. Both synchronous and asynchronous strategies have been suggested to manage this problem. Creating a low skew clock tree for synchronous inter-block pipeline stages is a significant challenge. Asynchronous interconnect does not require a global clock, and therefore, it has a potential advantage in terms of design effort. This paper presents an asynchronous interconnect design that can be implemented using a standard application-specific IC flow. This design is considered across a range of IC interconnect scenarios. The results demonstrate that there is a region of the design space where the implementation provides an advantage over a synchronous interconnect by removing the need for clocked inter-block pipeline stages, while maintaining high throughput. Further results demonstrate a computer-aided design tool enhancement that would significantly increase this space. A detailed comparison of power, area, and latency of the two strategies is also provided for a range of IC scenarios.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2008.917545