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Impact of Device Layout and Annealing Process During the Passivation of Interface States in Presence of Silicon Nitride Layers : International Conference on Microelectronic Test Structures
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Published in: | IEEE transactions on semiconductor manufacturing 2008, Vol.21 (2), p.195-200 |
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Main Authors: | , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Online Access: | Get full text |
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ISSN: | 0894-6507 1558-2345 |