A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors

This paper presents an effective reconfiguration scheme consisting of detailed spare replacement, processor placement, routing, and switch programming mechanisms. A new switch programming scheme is proposed to reduce the hardware overhead of reconfiguration. A thorough yield simulation tool has been...

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Bibliographic Details
Published in:IEEE transactions on computers 1997-12, Vol.46 (12), p.1363-1371
Main Authors: Yung-Yuan Chen, Upadhyaya, S.J., Ching-Hwa Cheng
Format: Article
Language:English
Subjects:
Analytical models
Applied sciences
Computers, microcomputers
Degradation
Electronics
Exact sciences and technology
Fault tolerance
Hardware
Logic arrays
Performance analysis
Redundancy
Routing
Switches
Testing
Very large scale integration
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Summary:This paper presents an effective reconfiguration scheme consisting of detailed spare replacement, processor placement, routing, and switch programming mechanisms. A new switch programming scheme is proposed to reduce the hardware overhead of reconfiguration. A thorough yield simulation tool has been developed for accurate prediction of yield by considering the effects of defect clusters and switching network failures. This yield simulation tool can also be used to obtain the information on the performance degradation, spare replacement, processor placement, routing and the switch programming algorithm survival probability.
ISSN:0018-9340
1557-9956
DOI:10.1109/12.641936