Intrinsic MOSFET parameter fluctuations due to random dopant placement

• Published in: IEEE transactions on very large scale integration (VLSI) systems 1997-12, Vol.5 (4), p.369-376
• Main Authors: Xinghai Tang, De, V.K., Meindl, J.D.
• Format: Article
• Language: English
• Subjects: Applied sciences; CMOS technology; Delay; Electronics; Exact sciences and technology; Fluctuations; Monte Carlo methods; MOSFET circuits; Power dissipation; Power semiconductor switches; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductor process modeling; Subthreshold current; Threshold voltage; Transistors
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/92.645063

Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultrasmall-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte Carlo simulator. These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard and maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40 and 600 mV, 10 and 100%, 2 and 20 mV/dec, and 10 and 10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V complementary metal-oxide-semiconductor (CMOS) technology generation with 1.3-64 billion transistors on a chip in 2010. While these deviations can be reduced to some degree by selecting optimal values of channel width, the associated penalties in dynamic and static power, and in packing density demand improved MOSFET structures aimed at minimizing parameter deviations.