LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS

• Published in: IEEE journal of solid-state circuits 2009-02, Vol.44 (2), p.436-449
• Main Authors: Kossel, M., Morf, T., Weiss, J., Buchmann, P., Menolfi, C., Toifl, T., Schmatz, M.L.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); CMOS; CMOS radio-frequency integrated circuits; CMOS technology; Coiling; Coils; Design. Technologies. Operation analysis. Testing; Dividers; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Frequency; Inductance; Inductors; Integrated circuits; integrated transformer; Locking; Magnetic devices; Oscillators; Oscillators, resonators, synthetizers; Phase locked loops; Q factor; self- and mutual-inductance switching; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; switched inductor coil; Switches; Switching; Switching loss; Wideband; wideband LC PLL
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2008.2011041

A wideband LC PLL in 45-nm SOI CMOS technology is presented that has a center frequency of 12.4 GHz and 1.2 octave locking range. The wideband operation is achieved by switching mutual inductances within the inductor coil of the LC oscillator. To minimize resistive switching losses, the inductor coil consists of a non-switchable primary coil and two isolated secondary coils with series switches. When the switches are closed, the overall inductance reduces because of the switched mutual inductances. Three inductor bands, each consisting of 16 switched capacitor sub-bands, span a frequency range from 7.3 to 17.5 GHz. The in-band phase noise measured after a 1/4 divider is better than -107 dBc/Hz at 1 MHz offset frequency in the entire locking range. The PLL is fully differential and its core has a power consumption of 25 mW at the highest oscillation frequency.