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Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 mum) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconne...

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Published in:IEEE transactions on electronics packaging manufacturing 2009-04, Vol.32 (2), p.106-114
Main Authors: Sangil Lee, Myung Jin Yim, Master, R.N., Wong, C.P., Baldwin, D.F.
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Language:English
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cited_by cdi_FETCH-LOGICAL-c385t-eaba39678a9b936bd6ea26f9dcc920bacdf23016aecc52edb809577cf7f04ef93
cites cdi_FETCH-LOGICAL-c385t-eaba39678a9b936bd6ea26f9dcc920bacdf23016aecc52edb809577cf7f04ef93
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container_title IEEE transactions on electronics packaging manufacturing
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creator Sangil Lee
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description The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 mum) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite of such challenges, a high yield, reliable assembly process (>99.99%) has been achieved using commercial no-flow underfill material with a high I/O, fine-pitch FCIP. This has been obtained using design of experiments with physical interpretation techniques. Statistical analysis determined what assembly conditions should be used in order to achieve robust interconnects without disrupting the FCIP interconnect structure. However, the resulting high yield process had the side effect of causing a large number of voids in the FCIP assemblies. Parametric studies were conducted to develop assembly process conditions that would minimize the number of voids in the FCIP induced by thermal effects. This work has resulted in a significant reduction in the number of underfill voids. This paper presents systematic studies into yield characterization, void formation characterization, and void reduction through the use of structured experimentation which was designed to improve assembly yield and to minimize the number of voids, respectively, in FCIP assemblies.
doi_str_mv 10.1109/TEPM.2009.2015592
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source IEEE Electronic Library (IEL) Journals
subjects Applied sciences
Assembly
Assembly systems
Assembly yield
Chip formation
Chips
Degradation
Density
Design of experiments
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
fine pitch
Flip chip
high I/O density
Integrated circuits
Joining materials
Materials reliability
Materials science and technology
no-flow underfill
Organic materials
Reduction
reliability
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Side effects
Silicon
Soldering
Statistical analysis
Studies
void formation
Voids
title Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill
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