Interests and Limitations of Technology Scaling for Subthreshold Logic

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2009-10, Vol.17 (10), p.1508-1519
• Main Authors: Bol, D., Ambroise, R., Flandre, D., Legat, J.-D.
• Format: Article
• Language: English
• Subjects: Applied sciences; Channels; Circuits; CMOS digital integrated circuits; CMOS technology; Degradation; Delay; Design. Technologies. Operation analysis. Testing; Dynamics; Electric potential; Electronics; Energy consumption; Energy efficiency; Exact sciences and technology; Integrated circuits; Logic; Logic circuits; Logic devices; MOSFET circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; subthreshold logic; technology scaling; Throughput; ultralow power (ULP); variability; Very large scale integration; Voltage
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2008.2005413

Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded subthreshold swing and delay variability. Moreover, for low-throughput applications (10-100 kHz), this limitation is worsened by the increase of minimum supply voltage to achieve sufficient functional yield, which results in bad energy efficiency starting at 0.13 mum node. Upsizing the channel length is proposed as a straightforward circuit-level technique to efficiently mitigate these effects. At 32 nm node, this technique reduces energy per operation by 60% at medium throughput and by two orders of magnitude at low throughput.