3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

• Published in: IEEE transactions on microwave theory and techniques 2010-01, Vol.58 (1), p.48-56
• Main Authors: Lahiji, R.R., Sharifi, H., Katehi, L.P.B., Mohammadi, S.
• Format: Article
• Language: English
• Subjects: 3-D integration; Amplification; Amplifiers; Applied sciences; BiCMOS integrated circuits; Chips (electronics); Circuit properties; Circuits; CMOS; CMOS process; CMOS technology; Compressing; Coplanar transmission lines; Coplanar waveguide (CPW); Coplanar waveguides; Design. Technologies. Operation analysis. Testing; Dielectric loss measurement; Dielectric substrates; Distributed parameter circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Integrated circuit interconnections; Integrated circuits; low-noise amplifier (LNA); Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits; Microwaves; Noise levels; parylene-N; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transmission line measurements; Transmission lines; vertical interconnect
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2009.2036394

Parylene-N is used as a dielectric layer to create ultra low-loss 3-D vertical interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D vertical interconnect through a 15-¿ m-thick parylene-N layer and 0.56 dB/mm for a 50-¿ CPW line on the parylene-N layer (compared to 1.85 dB/mm on a standard CMOS substrate) are measured at 40 GHz. L-shaped, U-shaped, and T-junction CPW structures are also fabricated with under passes that eliminate the discontinuities arisen from the slot-line mode and are characterized up to 40 GHz. A 3-D low-noise amplifier using these post-processed structures on a 0.13-¿m CMOS technology is also presented along with the investigation of parasitic effects for accurate simulation of such a 3-D circuit. The 3-D circuit implementation reduces the attenuation per unit length of the transmission lines, while preserving the CMOS chip area (in this specific design) by approximately 25%. The 3-D amplifier measures a gain of 13 dB at 2 GHz with 3-dB bandwidth of 500 MHz, noise figure of 3.3 dB, and output 1-dB compression point of +4.6 dBm. Room-temperature processing, simple fabrication, low-loss performance, and compatibility with the CMOS process make this technology a suitable choice for future 3-D CMOS and BiCMOS monolithic microwave integrated circuit applications that currently suffer from high substrate loss and crosstalk.