Fully synthesised decimation filter for delta-sigma A/D converters

• Published in: International journal of electronics 2010-06, Vol.97 (6), p.663-676
• Main Authors: Roh, Hyungdong, Byun, Sanho, Choi, Youngkil, Roh, Jeongjin
• Format: Article
• Language: English
• Subjects: A/D converter; Applied sciences; Circuit properties; CMOS; Converters; Data converters; decimation filter; Design engineering; Design. Technologies. Operation analysis. Testing; Digital; Digital circuits; Digital electronics; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Experiments; Filters; Frequency filters; Hardware; Integrated circuits; Multiplication; Redesign; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors
• ISSN: 0020-7217; 1362-3060
• DOI: 10.1080/00207211003697830

Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a fully synthesised digital decimation filter that provides a time-to-market advantage. The filter consists of a cascaded integrator-comb filter and two cascaded half-band FIR filters. A canonical signed-digit representation of the filter coefficients is used to minimise the area and to reduce the hardware complexity of the multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated by using 0.25-μm CMOS technology with an active area of 1.36 mm 2 and shows 4.4 mW power consumption at a clock rate of 2.8224 MHz. Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time. This is possible because the filter does not have process-dependent ROM or RAM circuits.