A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery s...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2010-06, Vol.45 (6), p.1111-1121
Main Authors: Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Martins, Rui Paulo, Maloberti, Franco
Format: Article
Language:English
Subjects:
Applied sciences
Charge
Charge-recovery
Circuit properties
CMOS
Conversion
Design. Technologies. Operation analysis. Testing
Digital video broadcasting
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Energy consumption
Exact sciences and technology
Integrated circuits
Laboratories
Linearity
Noise levels
Pipelines
Power dissipation
Power generation
reference-free
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
Silicon compounds
switched technique
Switching
Synthetic aperture radar
Very large scale integration
Voltage
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Description
Summary:A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2010.2048498