All-Optical Half-Adder Using All-Optical XOR and AND Gates for Optical Generation of "Sum" and "Carry"

• Published in: Fiber and integrated optics 2010-07, Vol.29 (4), p.254-271
• Main Authors: Menezes, J. W. M., Fraga, W. B., Ferreira, A. C., Guimarães, G. F., Filho, A. F. G. F., Sobrinho, C. S., Sombra, A. S. B.
• Format: Article
• Language: English
• Subjects: All optical circuits; Applied sciences; Circuit properties; Computer simulation; Directional couplers; Electric, optical and optoelectronic circuits; Electronics; Exact sciences and technology; Fiber optics; Gates (circuits); Integrated circuits; Integrated optics. Optical fibers and wave guides; Logic; Mathematical analysis; Mathematical models; non-linear coupler; Nonlinearity; Optical and optoelectronic circuits; Optical fibers; optical half-adder; Optical telecommunications; Simulation; Switching and signalling; Systems, networks and services of telecommunications; Telecommunications; Telecommunications and information theory; Telecommunications systems
• ISSN: 0146-8030; 1096-4681
• DOI: 10.1080/01468030.2010.485290

In this article, a numerical simulation study using the symmetric planar three-core non-linear directional coupler, operating with a short light pulse (2 ps), for the implementation of an all-optical half-adder is presented. The half-adder is the key building block for many digital processing functions such as shift register, binary counter, and serial parallel data converters. Optical couplers are an important component for application in optical fiber telecommunication systems and all integrated optical circuits because of very high switching speeds (as high as the femto-second range). In this numerical simulation, the symmetric planar three-core non-linear directional coupler presents a planar symmetrical structure with three cores in a parallel equidistant arrangement, three logical inputs (CP, A, and B), and two output logic functions (C and S). The CP(ΔΦ) input is a control pulse with a phase difference ΔΦ = Δθπ (0 ≤ Δθ ≤ 2) between inputs A and B (logical inputs of the half-adder) and one amplitude discriminator circuit. The half-adder uses two output logic functions of Sum(S) and Carry(C), which can be demonstrated by using XOR and AND gates, respectively. For the half-adder, the phase [ΔΦMIN, ΔΦMAX] intervals are studied, allowing the operation of the device as a half-adder. For the selected range of CP(ΔΦ BETTER ), the extinction ratio was studied, the compression factors for both Sum(S) and Carry(C) outputs of the symmetric planar three-core non-linear directional coupler.