Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction Schemes

Saved in:
Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2010-08, Vol.18 (8), p.1234-1238
Main Authors: LEE, Chiou-Yng, PRAMOD KUMAR MEHER, JAGDISH CHANDRA PATRA
Format: Article
Language:English
Subjects:
Applied sciences
Circuit properties
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2009.2020593