Design Optimization of FinFET Domino Logic Considering the Width Quantization Property

Design optimization of FinFET domino logic is particularly challenging due to the unique width quantization property of FinFET devices. Since the keeper device in domino logic is sized based on the leakage current of the pull-down network (PDN) (to meet the noise margin constraint), a reliable stati...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on electron devices 2010-11, Vol.57 (11), p.2934-2943
Main Authors: Rasouli, S H, Dadgour, H F, Endo, K, Koike, H, Banerjee, K
Format: Article
Language:English
Subjects:
Applied sciences
Circuit properties
Design optimization
Devices
Digital circuits
Domino logic
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Field programmable gate arrays
FinFET
FinFETs
Gates
Leakage current
leakage estimation
Logic
Methodology
Noise
Partial discharges
Performance evaluation
Quantization
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Sizing
Threshold voltage
Transistors
width quantization
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Design optimization of FinFET domino logic is particularly challenging due to the unique width quantization property of FinFET devices. Since the keeper device in domino logic is sized based on the leakage current of the pull-down network (PDN) (to meet the noise margin constraint), a reliable statistical framework is required to accurately estimate the domino gate leakage current. Considering the width quantization property, this paper presents such a statistical framework, which provides a reliable design window for keeper sizing to meet the noise margin constraint (for the practical range of threshold voltage variation in sub-32-nm technology nodes). On the other hand, the width quantization property restricts the design optimization (including power/performance characteristics) typically achieved via continuous keeper sizing in planar-CMOS domino logic designs. To cope with this restriction, this paper also introduces a novel methodology for FinFET-based keeper design, which exploits the exclusive property of FinFET devices (capacitive coupling between the front gate and the back gate in a four-terminal FinFET) to simultaneously achieve higher performance and lower power consumption. Using this new methodology, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the PDN, but gradually becomes stronger to provide a higher noise margin.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2010.2076374