An x86-64 Core in 32 nm SOI CMOS

• Published in: IEEE journal of solid-state circuits 2011-01, Vol.46 (1), p.162-172
• Main Authors: Jotwani, R, Sundaram, S, Kosonocky, S, Schaefer, A, Andrade, V F, Novak, A, Naffziger, S
• Format: Article
• Language: English
• Subjects: 64-bit architecture; 8T RAMcell; Applied sciences; Array design techniques; Arrays; Chip formation; Circuits; clock power reduction; Clocks; CMOS; Delay; Design. Technologies. Operation analysis. Testing; electromigration; Electronics; Exact sciences and technology; Gating and risering; Integrated circuits; Integrated circuits by function (including memories and processors); Logic gates; low power; Metals; power gating; power monitor; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Strain; Transistors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2010.2080530

This paper describes the 32 nm implementation of an AMD x86-64 core. It occupies 9.69 mm 2 , contains more than 35 million transistors (excluding L2 cache), and operates at frequencies in excess of 3 GHz. This AMD chip is fabricated in Global Foundries' 32 nm SOI and uses high-K metal gate technology. The process uses dual strain liners and eSiGe (embedded Silicon Germanium) to improve performance. Transistors are fabricated in various threshold voltages and lengths to facilitate performance/leakage tradeoffs. The core incorporates numerous design and power improvements to enable an operating range of 2.5 W to 25 W and a near zero-power gated state, which makes the core well-suited to a broad range of mobile and desktop products including multicore SOC designs.