Monte Carlo optimization of superconducting complementary output switching logic circuits

• Published in: IEEE transactions on applied superconductivity 1998-09, Vol.8 (3), p.104-119
• Main Authors: Jeffery, M., Perold, W.J., Zuoqin Wang, van Duzer, T.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; Circuit simulation; Clocks; Design optimization; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Frequency; Integrated circuits; Josephson junctions; Logic circuits; Logic design; Monte Carlo methods; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Superconducting logic circuits; Switching, multiplexing, switched capacity circuits; Voltage
• ISSN: 1051-8223; 1558-2515
• DOI: 10.1109/77.712141

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix.